The present invention generally relates to processing of Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) frames, and more specifically, to a processor designed to multiplex channelized data onto a SONET/SDH frame.
Virtual concatenation defines an efficient way to utilize the SONET/SDH bandwidth. It is extended based on contiguous concatenation. In contiguous concatenation, certain number of STS-1 timeslots are grouped together to form a larger pipe. Because of various practical and technical constraints, the size of a contiguously concatenated channel is limited to 3N, where N is 1, 4, 16, 64, etc. As a result, if a user only needs 5× the bandwidth of a STS-1 channel, s/he will have to subscribe for a STS-12c channel, thereby wasting both bandwidth and/or money. In virtual concatenation, any number of STS-1 or STS-3c timeslots can be grouped together to provide a larger pipe. Hence, the total available bandwidth can be more efficiently managed and used. Although different timeslots may go through different paths with different propagation delays, synchronization is maintained by cooperation between both the transmit and the receive ends such that the virtually concatenated channel looks like a contiguously concatenated channel.
The ANSI T1-X1.5 is a new and evolving standard on virtual concatenation. Hence, there are currently no devices that fully support this standard. Therefore, it would be desirable to provide a system which is capable of utilizing and taking advantage of the benefits offered by virtual concatenation.